14. Coprocessor 0
The XContext register is for use with the XTLB refill handler, which loads TLB entries for references to a 64-bit address space, and is included solely for operating system use. The operating system sets the PTE base field in the register, as needed. Normally, the operating system uses the Context register to address the current page map, which resides in the kernel-mapped segment kseg3.
Figure 14-19 shows the format of the XContext register; Table 14-17 describes the XContext register fields.
Figure 14-19 XContext Register Format
The 31-bit BadVPN2 field holds bits 43:13 of the virtual address that caused the TLB miss; bit 12 is excluded because a single TLB entry maps to an even-odd page pair. For a 4-Kbyte page size, this format may be used directly to address the pair-table of 8-byte PTEs. For other page and PTE sizes, shifting and masking this value produces the appropriate address.
Figure 14-19; see page 224 of Errata.
